Micron has launched a production version of the 12 layer HBM3E chip suitable for the next generation of artificial intelligence (AI) GPUs, with a memory stack capacity of up to 36GB and speeds exceeding 9.2Gb/s. Micron stated that it is currently delivering the production portable 12 layer fifth generation HBM (HBM3E) to important partners in the AI industry chain for verification procedures.

Micron officially announced the launch of HBM3E memory with a 12 layer stack on September 9th. The new product has a capacity of 36GB and is designed for cutting-edge processors for AI and HPC (high-performance computing) workloads, such as Nvidia's H200 and B100/B200 GPUs.

Micron's 12 layer HBM3E memory stack has a capacity of 36GB, which is 50% higher than the previous 8-layer version (24GB). The increase in capacity enables data centers to run larger AI models on a single processor. This feature eliminates the need for frequent CPU offloading, reduces communication latency between GPUs, and speeds up data processing.

In terms of performance, Micron's 12 layer HBM3E stack can provide memory bandwidth exceeding 1.2TB/s and data transfer rates exceeding 9.2Gb/s. According to Micron, the company's HBM3E not only provides 50% more memory capacity than its competitors, but also consumes less power than the 8-layer HBM3E stack.

Micron's 12 layer HBM3E includes a fully programmable memory built-in self-test (MBIST) system to ensure faster product time to market and reliability for customers. This technology can simulate system level traffic at full speed, enabling comprehensive testing and faster validation of new systems.

Micron's HBM3E memory devices are compatible with TSMC's CoWoS packaging technology, which is widely used in AI processor packages such as Nvidia's H100 and H200.

It is reported that Micron has started developing its next-generation memory solutions, including HBM4 and HBM4E. These upcoming memory types will continue to meet the growing demand for advanced memory in AI processors, including Nvidia GPUs based on Blackwell and Rubin architectures.