According to Reuters, the Santa Clara, California-based semiconductor manufacturing tool manufacturer Applied Materials Inc. (Applied Materials Inc) on Monday introduced a new technology designed to alleviate the speed bottleneck of computer chips.
The report pointed out that computer chips are made up of switches called transistors that help them perform digital logic of 1s and 0s. But these transistors must be connected with conductive metal to send and receive electrical signals. This metal is usually tungsten. Chip manufacturers choose this metal because it has low resistance and allows electrons to move quickly.
According to the official press release of Applied Materials, although the development of photolithography technology has helped reduce the contact vias of transistors, the traditional method of filling vias with contact metal has become a key bottleneck for PPAC.
The announcement stated that, traditionally, transistor contacts are formed in a multilayer process. The contact hole is first lined with an adhesion and barrier layer made of titanium nitride, then a nucleation layer is deposited, and finally the remaining space is filled with tungsten, which is the preferred contact metal due to its low resistivity.
But at the 7nm node, the diameter of the contact hole is only about 20nm. The lining barrier layer and the nucleation layer account for about 75% of the volume of the via, while tungsten only accounts for about 25% of the volume. The thin tungsten wire has a high contact resistance, which will become the main bottleneck for PPAC and further 2D scaling.
"With the advent of EUV, we need to solve some key material engineering challenges in order for 2D scaling to continue," said Dan Hutcheson, chairman and CEO of VLSIresearch. Linear barrier agents have become the equivalent of atherosclerotic plaque products in our industry, causing the chip to lose the electron flow required to achieve optimal performance. Applied Materials' selective tungsten is the breakthrough we have been waiting for. "
According to reports, if the tungsten required in the connection area is coated with several other materials. These other materials increase resistance and slow down the connection speed. Applied Materials said on Monday that it has developed a new process that eliminates the need for other materials and only uses tungsten at the connection to speed up the connection.
Applied Materials pointed out that the company's selective tungsten technology (selective tungsten technology) is an integrated material solution that combines a variety of process technologies in the original high vacuum environment, which is many times cleaner than the clean room itself . The chip is subjected to atomic-level surface treatment and a unique deposition process is used to selectively deposit tungsten atoms in the contact vias to form a perfect bottom-up filling without delamination, seams or voids.
Kevin Moraes, vice president of Applied's semiconductor products division, said in a statement that chip features "have become smaller and smaller, so that we have reached the physical limits of conventional materials and material engineering technology."
Applied said it has signed up to "multiple leading customers worldwide" for this technology, but did not disclose their names.
Applied Materials launches the biggest material revolution in interconnect technology in 15 years
In 2014, Applied Materials introduced what they believe is the biggest change in interconnection technology in 15 years.
Applied Materials has launched the AppliedEnduraVoltaCVDCobalt system, which is currently the only system capable of realizing cobalt thin films through chemical vapor deposition in the logic chip copper interconnect process. There are two applications of cobalt film in the copper process, flat liner (Liner) and selective cover layer (CappingLayer), which increase the reliability of copper interconnects by an order of magnitude. This application is the most significant change in copper interconnect technology materials in 15 years.
Dr. Randhir Thakur, Executive Vice President and General Manager of the Semiconductor Division of Applied Materials, pointed out: “For device manufacturers, with hundreds of millions of transistor circuits connected to the chip, the performance and reliability of the wiring are extremely important. With Moore’s Law With the advancement of technology, the size of the circuit is getting smaller and smaller, it is more necessary to reduce the gap that affects the operation of the device and prevent electromigration failure." Based on Applied Materials' industry-leading precision material engineering technology, the EnduraVolta system can overcome the yield limit by providing CVD-based flat liners and selective overlays, and help our customers advance copper interconnect technology To 28 nanometers and below.
The cobalt process based on the EnduraVoltaCVD system includes two main process steps. The first step is to deposit a flat and thin cobalt liner film. Compared with the typical copper interconnection process, the application of cobalt can provide more space for filling the limited interconnection area with copper. This step integrates the pre-clean (Pre-clean) / barrier layer (, PVDBarrier) / cobalt liner layer (CVDLiner) / copper seed layer (CuSeed) process on the same platform under ultra-high vacuum to improve the performance and Yield rate.
In the second step, after the copper chemical mechanical polishing (CuCMP), a layer of selective CVD cobalt coating is deposited to improve the contact interface, thereby increasing the reliability of the device by 80 times.
Dr. Sundar Ramamurthy, Vice President and General Manager of the Metal Deposition Products Division of Applied Materials, pointed out: “The unique CVD cobalt process of Applied Materials is a solution based on material innovation. These materials and processes have been developed in the past ten years. Innovation is being accepted by our customers and used to manufacture high-performance mobile and server chips.